The use of cache subsystems in microcomputer systems leads to a number of attractive operating advantages. Microcomputer systems employing cache subsystems are in effect dual bus microcomputers. The CPU and cache subsystem are connected together via what can be referred to as a CPU local bus. Separate from the CPU local bus is a system bus to which other devices (I/O devices, additional memory, etc.) can be connected. The presence of the cache subsystem relieves the system bus from any read memory access to the extent that the information sought is also found in the cache subsystem. Because not all desired information will be found in the cache subsystem, and write operations are usually directed to both the cache subsystem and to memory, there must of course be some connection between the system bus and the CPU local bus.
Under certain circumstances, however, the CPU and/or the cache controller is arranged to inhibit cache operations for certain commands. For example, the 80386 CPU includes a LOCK signal for multiprocessor and multimaster designs. The signal tells other bus masters that the processor is performing a multiple bus cycle operation that must not be interrupted. The 80386 for example automatically asserts LOCK when it updates the segment descriptor and page tables, during interrupt acknowledge bus cycles, and when it executes the Exchange instruction. The manufacturer of the 80386 recommends that the LOCK output of the 80386 be tied to a LOCK input of a cache controller. The cache controller, since it has visibility of not only the CPU local bus (on which the cache memory resides) but also the system bus (on which main and other memory resides) has the capability of allowing a cache operation or inhibiting the cache operation. Typically, the cache controller (such as an 83285) will prevent a cache operation for any cycle on which the LOCK input is asserted.
The characteristics of the 80386 and 83285 devices are described in "Microprocessor and Peripheral Handbook", "83285 High Performance 32-Bit Cache Controller" and "Introduction to the 80386" and the 80386 Hardware Reference Manual, all published by Intel. The "83285 High Performance 32-Bit Cache Controller" indicates (Section 3.4.2) that when the LOCK output (of the 80386) is asserted, a sequence is run on the system bus regardless of whether any locations referenced in the sequence reside in cache.
In other words, a read hit will be run as if it were a read miss.
Notwithstanding the foregoing, however, in most Personal Computer (PC) environments, descriptors are not shared between system processors. As a result, the effect of assertion of the LOCK signal causes a significant performance degradation, especially when operating in an 80386 protect mode. This performance degradation comes about because the 83285 cache controller treats all locked operations as non-cacheable.